IdeaWell

Project ideas from Hacker News discussions.

RISC-V Is Sloooow

Original Article

Hacker News Discussion

📝 Discussion Summary (Click to expand)

1. The ISA is not the culprit – silicon matters most

“Don’t blame the ISA – blame the silicon implementations AND the software with no architecture‑specific optimisations.” – rbanffy
“They indeed do not blame the architecture but the available silicon implementations.” – dmitrygr

2. RISC‑V is expected to catch up, but only with new silicon

“RISC‑V will get there, eventually.” – rbanffy
“Fast, RVA23‑compatible micro‑architectures already exist… the first RVA23‑compatible chips… will ship this summer.” – newpavlov

3. Compiler and software support is the real bottleneck

“The optimisations that’d be applied to ARM and MIPS would be equally applicable to RISC‑V.” – cogman10
“One thing compilers still struggle with is exploiting weird micro‑architectural quirks or timing behaviours that aren’t obvious from the ISA spec.” – hrmtst93837

4. The modular, optional‑extension design fragments performance

“RISC‑V lacks a bunch of really useful relatively easy to implement instructions and most extensions are truly optional so you can’t rely on them.” – newpavlov
“RVA23 offers a very similar feature‑set to x86‑64v4.” – LeFantome
“Misaligned loads and stores might execute extremely slowly… standard software distributions should assume their existence only for correctness, not for performance.” – camel‑cdr

5. Market forces and investment gaps keep RISC‑V behind

“Intel, AMD, Apple, Qualcomm, or Nvidia could redirect their existing teams to design a high‑performance RISC‑V CPU.” – lizknope
“The most promising RISC‑V companies today have not set out to compete directly with Intel, AMD, Apple or Samsung, but are targeting a niche such as AI, HPC and/or high‑end embedded such as automotive.” – findecanor
“China is likely where it would come from – ARM and x86 are owned by Western companies.” – benced

These five themes capture the dominant viewpoints in the discussion: performance is a silicon issue, RISC‑V will improve with new chips, software/compilers need better support, the ISA’s optional‑extension model causes fragmentation, and the lack of large‑scale investment keeps RISC‑V behind the incumbents.

🚀 Project Ideas

RISC‑V Performance Dashboard

Summary

  • Aggregates real‑world benchmarks (Geekbench, SPEC, AI workloads) for every available RISC‑V board.
  • Filters by price, core count, AI performance, memory bandwidth, and silicon vendor.
  • Provides curated “best‑value” recommendations for developers and hobbyists.

Details

Key Value
Target Audience RISC‑V developers, hobbyists, system integrators
Core Feature Interactive benchmark database + recommendation engine
Tech Stack React + Node.js, PostgreSQL, Docker for data ingestion
Difficulty Medium
Monetization Revenue‑ready: tiered subscription (free, pro, enterprise)

Notes

  • Users repeatedly ask “What is the current fastest platform that isn’t exorbitantly expensive?” (e.g., “What is the current fastest ppc64le implementation that isn’t exorbitantly expensive?”).
  • The dashboard would turn anecdotal comparisons (“Banana Pi is slow”) into data‑driven decisions.
  • It fuels discussion on hardware selection and can be integrated into build pipelines.

RISC‑V Build Acceleration Service

Summary

  • Cloud‑based CI that builds Fedora (or other distros) packages natively on RISC‑V hardware.
  • Uses ccache, parallel linkers, and pre‑built toolchains to cut build times from 10 h to <2 h.
  • Provides a web UI for monitoring, logs, and artifact storage.

Details

Key Value
Target Audience Distribution maintainers, open‑source projects targeting RISC‑V
Core Feature Native RISC‑V build farm with caching and auto‑scaling
Tech Stack Kubernetes, Docker, GitLab CI, Redis for caching
Difficulty High
Monetization Revenue‑ready: pay‑per‑build or subscription for enterprise use

Notes

  • “Build time on target hardware matters when you’re re‑building an entire Linux distribution” (user poulpy123).
  • The service addresses the pain of long build cycles and the lack of native build infrastructure.
  • It can be marketed to Fedora, Arch, and other projects needing reliable RISC‑V builds.

RISC‑V Compiler Optimizer

Summary

  • A CLI tool that profiles a target RISC‑V silicon and auto‑generates optimal GCC/LLVM flags and backend patches.
  • Supports misaligned load tuning, vector extension selection, and memory‑bandwidth aware scheduling.
  • Outputs a “profile file” that can be dropped into any build system.

Details

Key Value
Target Audience Compiler developers, performance engineers, system integrators
Core Feature Automated flag generation + backend patching
Tech Stack Rust, LLVM/Clang APIs, Docker for sandboxing
Difficulty Medium
Monetization Revenue‑ready: per‑license or SaaS model

Notes

  • Users complain about “compilers still struggle with exploiting weird microarchitectural quirks” (hrmtst93837).
  • The tool would reduce the need for manual tuning (“I had to tweak flags for each board”).
  • It can be integrated into the Build Acceleration Service for end‑to‑end performance.

RISC‑V Hardware Development Kit

Summary

  • A modular hardware kit that bundles a SiFive P550 or SpaceMIT K3 board, pre‑installed OS images, and a curated software stack.
  • Includes a quick‑start guide, benchmark scripts, and a cloud‑connected diagnostics panel.
  • Aimed at developers wanting to prototype high‑performance RISC‑V systems without custom silicon.

Details

Key Value
Target Audience Embedded developers, hobbyists, academic researchers
Core Feature Ready‑to‑use hardware + software bundle
Tech Stack ARM‑based firmware, Yocto, Docker for containerized demos
Difficulty Medium
Monetization Hobby (open source) with optional paid support packages

Notes

  • “I want a fast dev board that isn’t exorbitantly expensive” (user Aurornis).
  • The kit removes the “hard to find a fast board” pain point and provides a turnkey solution.
  • It can be sold through online marketplaces and supported by community forums.

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