🚀 Project Ideas
Generating project ideas…
Summary
- A lightweight runtime library that auto‑detects the exact set of RISC‑V extensions present on any MCU, exposing a simple API for conditional compilation.
- Eliminates guesswork and manual probing, letting developers write once‑run‑anywhere MCU code without fragile binary blobs.
Details
| Key |
Value |
| Target Audience |
Embedded developers targeting low‑cost MCU markets (electric‑blanket, IoT, automotive sensor nodes). |
| Core Feature |
Runtime detection of supported extensions (e.g., M, A, B, C, D, F, V, Z) and generation of optimized instruction stubs at build‑time; fallback mechanisms handled automatically. |
| Tech Stack |
Rust + no_std library; interfacing with GCC/LLVM via custom attribute macros; optional integration with Zephyr RTOS. |
| Difficulty |
Medium |
| Monetization |
Revenue-ready: Subscription |
Notes
- HN commenters repeatedly lament “you can’t know what extensions are present without probing”, and this tool answers that directly.
- Potential to become a standard utility for MCU vendors, driving widespread RISC‑V adoption in massive volume markets.
Summary
- A web‑based and CLI benchmark suite that runs user‑compiled binaries across a matrix of RISC‑V cores (RV32I, RV64GC, RVA23, etc.) and automatically reports code‑density, latency, and extension support gaps.
- Provides actionable insight into which extensions actually matter, helping developers avoid the “no sane way to query hardware” problem.
Details
| Key |
Value |
| Target Audience |
Compiler authors, OS kernel maintainers, and hardware architects testing portability. |
| Core Feature |
Multi‑target execution engine; automated detection of supported extensions via CSRs; performance & code‑density metrics per target; recommendation engine for optimal ISA profile. |
| Tech Stack |
Python backend; Docker containers running QEMU‑based RV cores; results stored in SQLite; web UI with Flask; integration with LLVM’s TD saturate. |
| Difficulty |
High |
| Monetization |
Revenue-ready: SaaS (COLLABORATIVE ACCESS) |
Notes
- Quote from a HN thread: “you can’t probe what your core actually supports” – RVMTH makes probing an automated, reproducible service.
- Solves the “no sane way to ship compatible performant code” dilemma, creating a discussion platform for ISA standardisation.
Summary
- An LLVM/GCC plugin that automatically rewrites uncompressed RISC‑V instructions into the densest possible compressed forms (C, C‑compressed, C‑compressed‑2) based on the target’s verified extension set, without manual programmer intervention.
- Directly tackles the frustration over RISC‑V’s variable‑length encoding being under‑utilised and perceived as complex.
Details
| Key |
Value |
| Target Audience |
Embedded firmware engineers and compiler maintainers who need maximal code density on constrained MCUs. |
| Core Feature |
Pattern‑matching back‑end pass that selects optimal compressed encodings, emits fallback stubs, and validates that generated code respects the target’s ISA profile. |
| Tech Stack |
LLVM Pass written in C++; optional front‑end hook for GCC; relies on the RISC‑V Compressed‑Instruction specification and a small runtime metadata file. |
| Difficulty |
High |
| Monetization |
Hobby |
Notes
- Referencing a comment that “compressed instructions aren’t a bad idea for small cores but add pipeline overhead”, this optimizer makes that trade‑off manageable automatically, which would be enthusiastically received by the community.
- Enables wider adoption in cost‑sensitive markets where code size is critical, creating discussion around standardising on a curated extension set.
